Research Article
Logical Effort to Study the Performance of 32-bit Heterogeneous Adder
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 65 - Issue 16 |
| Published: March 2013 |
| Authors: Neha Agarwal, Satyajit Anand |
10.5120/11010-6344
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Neha Agarwal, Satyajit Anand . Logical Effort to Study the Performance of 32-bit Heterogeneous Adder. International Journal of Computer Applications. 65, 16 (March 2013), 36-38. DOI=10.5120/11010-6344
@article{ 10.5120/11010-6344,
author = { Neha Agarwal,Satyajit Anand },
title = { Logical Effort to Study the Performance of 32-bit Heterogeneous Adder },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 65 },
number = { 16 },
pages = { 36-38 },
doi = { 10.5120/11010-6344 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Neha Agarwal
%A Satyajit Anand
%T Logical Effort to Study the Performance of 32-bit Heterogeneous Adder%T
%J International Journal of Computer Applications
%V 65
%N 16
%P 36-38
%R 10.5120/11010-6344
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The method of Logical Effort is an easy way to estimate the delay in a CMOS circuit. In this work application of Logical Effort on transistor level analysis of 32-bit heterogeneous adder architecture is designed and presented. Heterogeneous architecture consists of concatenation of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder unit. The efficiency of the Logical Effort model is analyzed by circuit simulation using Tanner EDA Tool.
References
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